The present invention relates to a semiconductor memory cell comprising at least 3 transistors, a transistor for read-out, a transistor for write-in and a junction-field-effect transistor for current control, a semiconductor memory cell comprising a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control and at least 1 diode, a semiconductor memory cell comprising at least 4 transistors, a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control and a third transistor for write-in, or a semiconductor memory cell comprising a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control, a third transistor for write-in and at least 1 diode, and a method of manufacturing the above semiconductor memory cell.
As a high-density semiconductor memory cell, there has been made available a dynamic semiconductor memory cell that can be said to be a single-transistor semiconductor memory cell including one transistor and one capacitor shown in FIG. 56. In the above semiconductor memory cell, an electric charge stored in the capacitor is required to be large enough to generate a sufficiently large voltage change on a bit line. However, as the planar dimensions of the semiconductor memory cell are reduced, the capacitor formed in a parallel planar shape decreases in size, which causes a new problem that, when information which is stored as an electric charge in the capacitor of the memory cell is read out, the read-out information is buried in noise, or that only a small voltage change is generated on the bit line since the stray capacitance of the bit line increases each time a new generation of the semiconductor memory cell is introduced. As means for solving the above problems, there has been proposed a dynamic semiconductor memory cell having a trench capacitor cell structure shown in FIG. 57 or a stacked capacitor cell structure. Since, however, the fabrication-related technology has its own limits on the depth of the trench (or the groove) or the height of the stack, the capacitance of the capacitor is also limited. For this reason, dynamic semiconductor memory cells having the above structures are said to reach the limit of dimensions smaller than those of the low sub-micron rules unless expensive new materials are introduced for the capacitor.
In the planar dimensions smaller than those of the low sub-micron rule, the transistor constituting the semiconductor memory cell also has problems of deterioration of the dielectric strength characteristic and punchthrough. There is therefore a large risk that current leakage arises even if the voltage applied to the semiconductor memory cell is still within a predetermined range. When a semiconductor memory cell is made infinitesimal in size, therefore, it is difficult to normally operate the semiconductor memory cell having a conventional transistor structure.
For overcoming the above limit problems of the capacitor, the present applicant has proposed a semiconductor memory cell comprising two transistors or two transistors physically merged into one unit, as is disclosed in Japanese Patent Application No. 246264/1993 (Japanese Patent Laid-open No. 99251/1995), corresponding to U.S. Pat. No. 5,428,238. The semiconductor memory cell shown in FIGS. 15(A) and 15(B) of Japanese Patent Laid-Open No. 99251/1995 comprises a first semi-conductive region SC1 of a first conductivity type formed in a surface region of a semiconductor substrate or formed on an insulating substrate, a first conductive region SC2 formed in a surface region of the first semi-conductive region SC1 so as to form a rectifier junction together with the first semi-conductive region SC1, a second semi-conductive region SC3 of a second conductivity type formed in a surface region of the first semi-conductive region SC1 and spaced from the first conductive region SC2, a second conductive region SC4 formed in a surface region of the second semi-conductive region SC3 so as to form a rectifier junction together with the second semi-conductive region SC3, and a conductive gate G formed on a barrier layer so as to bridge the first semi-conductive region SC, and the second conductive region SC4 and so as to bridge the first conductive region SC2 and the second semi-conductive region SC3, the conductive gate G being connected to a first memory-cell-selecting line, the first conductive region SC2 being connected to an information write-in setting line, and the second conductive region SC4 being connected to a second memory-cell-selecting line.
The first semi-conductive region SC1 (to function as a channel forming region Ch2), the first conductive region SC2 (to function as one source/drain region), the second semi-conductive region SC3 (to function as the other source/drain region) and the conductive gate G constitute a switching transistor TR2. On the other hand, the second semi-conductive region SC3 (to function as a channel forming region Ch1), the first semi-conductive region SC1 (to function as one source/drain region), the second conductive region SC4 (to function as the other source/drain region) and the conductive gate G constitute an information storing transistor TR1.
When information is written in the above semiconductor memory cell, the switching transistor TR2 is brought into an on-state. As a result, the information is stored in the channel forming region Ch1 of the information storing transistor TR1 as a potential or as an electric charge. When the information is read out, a threshold voltage of the information storing transistor TR1 seen from the conductive gate G varies, depending upon the potential or the electric charge stored in the channel forming region Ch1 of the information storing transistor TR1. Therefore, when the information is read out, the storage state of the information storing transistor TR1 can be judged from the magnitude of a channel current (including a zero magnitude) by applying a properly selected potential to the conductive gate G. The information is read out by detecting the operation state of the information storing transistor TR1.
That is, when the information is read out, the information storing transistor TR1 is brought into an on-state or an off-state, depending upon the information stored therein. Since the second conductive region SC4 is connected to the second memory-cell-selecting line, a large current or a small current may flow in the information storing transistor TR1, depending upon the stored information (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d). In this way, the information stored in the semiconductor memory cell can be read out by utilizing the information storing transistor TR1.
However, when the information is read out, the semiconductor memory cell has no mechanism for controlling the current which flows through the first semi-conductive region SC1 sandwiched by the first conductive region SC2 and the second semi-conductive region SC3. Therefore, when the information stored in the information storing transistor TR1 is detected with the conductive gate G, only a small margin of the current which flows between the first semi-conductive region SC1 and the second conductive region SC4 is obtained, which causes a problem that the number of the semiconductor memory cells connected to the second memory-cell-selecting line (a bit line) is limited.
It is therefore an object of the present invention to provide a semiconductor memory cell which attains the stable performance of transistors, a large window (current difference) for reading out information stored therein and permits infinitesimal dimensions or to provide a logic semiconductor memory cell.
Further, it is an object of the present invention to provide a semiconductor memory cell comprising at least 3 transistors, a transistor for read-out, a transistor for write-in and a junction-field-effect transistor for current control, or a semiconductor memory cell comprising a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control and at least 1 diode.
Further, it is another object of the present invention to provide a semiconductor memory cell comprising at least 4 transistors, a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control and a third transistor for write-in, or a semiconductor memory cell comprising a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control, a third transistor for write-in and at least 1 diode.
It is further another object of the present invention to provide a semiconductor memory cell having the above various transistors and diode merged into one, and a process for the manufacture thereof.
As shown in principle drawings of FIGS. 1A, 1B, 5, 16A and 16B, for achieving the above object, according to a first aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control,
wherein:
(A-1) one source/drain region of the first transistor TR1 is connected to a predetermined potential,
(A-2) the other source/drain region of the first transistor TR1 has a common region with one source/drain region of the junction-field-effect transistor TR3,
(A-3) a gate region G1 of the first transistor TR1 is connected to a first memory-cell-selecting line,
(B-1) one source/drain region of the second transistor TR2 is connected to a second memory-cell-selecting line,
(B-2) the other source/drain region of the second transistor TR2 has a common region with a channel forming region CH1 of the first transistor TR1 and with a first gate region of the junction-field-effect transistor TR3,
(B-3) a gate region G2 of the second transistor TR2 is connected to the first memory-cell-selecting line,
(C-1) a second gate region of the junction-field-effect transistor TR3 faces the first gate region thereof through a channel region CH3 thereof, the channel region CH3 thereof being an extended region of the other source/drain region of the first transistor TR1, and
(C-2) the other source/drain region of the junction-field-effect transistor TR3 is positioned in the extended region of the other source/drain region of the first transistor TR1 via the channel region CH3.
As shown in a principle drawing of FIG. 1A, the semiconductor memory cell according to the first aspect of the present invention preferably has a configuration in which the second gate region of the junction-field-effect transistor TR3 is connected to a second predetermined potential, and the other source/drain region of the junction-field-effect transistor TR3 is connected to an information read-out line. Alternatively, as shown in a principle drawing of FIG. 1B, the semiconductor memory cell preferably has a configuration in which the second gate region of the junction-field-effect transistor TR3 is connected to a second predetermined potential, and a junction portion of the other source/drain region of the junction-field-effect transistor TR3 and one source/drain region of the second transistor TR2 forms a diode D. Alternatively, as shown in a principle drawing of FIG. 5, the semiconductor memory cell may further comprise a diode D, and preferably has a configuration in which the second gate region of the junction-field-effect transistor TR3 is connected to a second predetermined potential and in which the other source/drain region of the junction-field-effect transistor TR3 is connected to the second predetermined potential through the diode D. In the drawings, the first memory-cell-selecting line is referred to as xe2x80x9c1ST LINExe2x80x9d, and the second memory-cell-selecting line is referred to as xe2x80x9c2ND LINExe2x80x9d.
Further, as shown in a principle drawing of FIG. 7, the semiconductor memory cell according to the first aspect of the present invention preferably has a configuration in which the first gate region and the second gate region of the junction-field-effect transistor TR3 are connected to each other, a junction portion of the other source/drain region of the junction-field-effect transistor TR3 and one source/drain region of the second transistor TR2 forms a diode D, and one end of the diode D is connected to the second memory-cell-selecting line.
Further, as shown in principle drawings of FIGS. 16A and 16B, the semiconductor memory cell preferably has a configuration in which one source/drain region of the second transistor TR2 has a common region with the second gate region of the junction-field-effect transistor TR3. In this case, as shown in FIG. 16A, the semiconductor memory cell preferably has a configuration in which one source/drain region of the second transistor TR2 and the second gate region of the junction-field-effect transistor TR3 are connected to the second memory-cell-selecting line, and the other source/drain region of the junction-field-effect transistor TR3 is connected to an information read-out line. Alternatively, as shown in FIG. 16B, the semiconductor memory cell preferably has a configuration in which one source/drain region of the second transistor TR2 and the second gate region of the junction-field-effect transistor TR3 are connected to the second memory-cell-selecting line, a diode D is formed in the other source/drain region of the junction-field-effect transistor TR3, and one end of the diode D is connected to the second memory-cell-selecting line.
As shown in principle drawings of FIGS. 10 and 21, for achieving the above object, according to a second aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, a junction-field-effect transistor TR3 of a first conductivity type for current control, and a diode D,
wherein:
(A-1) one source/drain region of the first transistor TR1 has a common region with one source/drain region of the junction-field-effect transistor TR3,
(A-2) the other source/drain region of the first transistor TR1 is connected to a second memory-cell-selecting line through the diode D,
(A-3) a gate region G1 of the first transistor TR1 is connected to a first memory-cell-selecting line,
(B-1) one source/drain region of the second transistor TR2 is connected to the second memory-cell-selecting line,
(B-2) the other source/drain region of the second transistor TR2 has a common region with a channel forming region CH1 of the first transistor TR1 and with a first gate region of the junction-field-effect transistor TR3,
(B-3) a gate region G2 of the second transistor TR2 is connected to the first memory-cell-selecting line,
(C-1) a second gate region of the junction-field-effect transistor TR3 faces the first gate region thereof through a channel region CH3 thereof, the channel region CH3 thereof being an extended region of one source/drain region of the first transistor TR1, and
(C-2) the other source/drain region of the junction-field-effect-transistor TR3 is positioned in an extended region of the other source/drain region of the first transistor TR1 via the channel region CH3, and is connected to a predetermined potential.
As shown in principle drawings of FIGS. 10 and 21, the semiconductor memory cell according to the second aspect of the present invention preferably has a configuration in which the second gate region of the junction-field-effect transistor TR3 is connected to a second predetermined potential.
Alternatively, as shown in principle drawings of FIGS. 13 and 24, the semiconductor memory cell according to the second aspect of the present invention preferably has a configuration in which the second gate region of the junction-field-effect transistor TR3 is connected to the first gate region thereof. As shown in principle drawings of FIGS. 29A and 29B, the semiconductor memory cell according to the second aspect of the present invention further may comprise a third transistor TR4 of a second conductivity type for write-in, and preferably has a configuration in which the second gate region of the junction-field-effect transistor TR3 is connected to the first gate region thereof through the third transistor TR4.
For achieving the above object, according to a third aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control,
said semiconductor memory cell having;
(a) a first semi-conductive region SC1 having a second conductivity type,
(b) a second semi-conductive or conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 forming a rectifier junction together with the first region SC1,
(c) a third semi-conductive region SC3 formed in a surface region of the first region SC1 and spaced from the second region SC2, said third region SC3 having a first conductivity type,
(d) a fourth semi-conductive or conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 forming a rectifier junction together with the third region SC3, and
(e) a fifth semi-conductive or conductive region SC5 formed in a surface region of the third region SC3 and spaced from the fourth region SC4, said fifth region SC5 forming a rectifier junction together with the third region SC3,
wherein;
(A-1) source/drain regions of the first transistor TR1 are constituted of the second region SC2 and the third region SC3,
(A-2) a channel forming region CH1 of the first transistor TR1 is constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(A-3) a gate region G1 of the first transistor TR1 is formed on a barrier layer formed on the surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(B-1) source/drain regions of the second transistor TR2 are constituted of the first region SC1 and the fourth region SC4,
(B-2) a channel forming region CH2 of the second transistor TR2 is constituted of a surface region of the third region SC3 sandwiched by the first region SC1 and the fourth region SC4,
(B-3) a gate region G2 of the second transistor TR2 is formed on a barrier layer formed on the surface region of the third region SC3 sandwiched by the first region SC1 and the fourth region SC4,
(C-1) gate regions of the junction-field-effect transistor TR3 are constituted of the fifth region SC5 and a portion of the first region SC1 facing the fifth region SC5,
(C-2) a channel region CH3 of the junction-field-effect transistor TR3 is constituted of part of the third region SC3 sandwiched by the fifth region SC5 and said portion of the first region SC1,
(C-3) source/drain regions of the junction-field-effect transistor TR3 are constituted of the third region SC3 extending from both ends of the channel region CH3 of the junction-field-effect transistor TR3,
(D) the gate region G1 of the first transistor TR1 and the gate region G2 of the second transistor TR2 are connected to a first memory-cell-selecting line,
(E) the second region SC2 is connected to a predetermined potential,
(F) the fourth region SC4 is connected to a second memory-cell-selecting line, and
(G) the fifth region SC5 is connected to a second predetermined potential.
In a variant of the semiconductor memory cell according to the third aspect of the present invention, the fifth region SC5 may be connected to the first region SC1, in place of being connected to the second predetermined potential.
The semiconductor memory cell according to the third aspect of the present invention including the above variant preferably has a configuration in which a junction portion of the third region SC3 and the fourth region SC4 forms a diode D, and one source/drain region of the junction-field-effect transistor TR3 is connected to the second memory-cell-selecting line through the diode D.
Further, the semiconductor memory cell according to the third aspect of the present invention preferably has a configuration in which a diode D is formed on the surface region of the third region SC3 corresponding to (or functioning as) one source/drain region of the junction-field-effect transistor TR3, and one source/drain region of the junction-field-effect transistor TR3 is connected to the second predetermined potential through the diode D.
For achieving the above object, according to a fourth aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control,
said semiconductor memory cell having;
(a) a first semi-conductive region SC1 having a second conductivity type,
(b) a second semi-conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 having a first conductivity type,
(c) a third semi-conductive region SC3 formed in a surface region of the first region SC1 and spaced from the second region SC2, said third region SC3 having the first conductivity type,
(d) a fourth semi-conductive or conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 forming a rectifier junction together with the third region SC3, and
(e) a fifth semi-conductive or conductive region SC5 formed in a surface region of the second region SC2, said fifth region SC5 forming a rectifier junction together with the second region SC2,
wherein;
(A-1) source/drain regions of the first transistor TR1 are constituted of the second region SC2 and the third region SC3,
(A-2) a channel forming region CH1 of the first transistor TR1 is constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(A-3) a gate region G1 of the first transistor TR1 is formed on a barrier layer formed on the surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(B-1) source/drain regions of the second transistor TR2 are constituted of the first region SC1 and the fourth region SC4,
(B-2) a channel forming region CH2 of the second transistor TR2 is constituted of a surface region of the third region SC3 sandwiched by the first region SC1 and the fourth region SC4,
(B-3) a gate region G2 of the second transistor TR2 is formed on a barrier layer formed on the surface region of the third region SC3 sandwiched by the first region SC1 and the fourth region SC4,
(C-1) gate regions of the junction-field-effect transistor TR3 are constituted of the fifth region SC5 and a portion of the first region SC1 facing the fifth region SC5,
(C-2) a channel region CH3 of the junction-field-effect transistor TR3 is constituted of part of the second region SC2 sandwiched by the fifth region SC5 and said portion of the first region SC1,
(C-3) source/drain regions of the junction-field-effect transistor TR3 are constituted of the second region SC2 extending from both ends of the channel region CH3 of the junction-field-effect transistor TR3,
(D) the gate region G1 of the first transistor TR1 and the gate region G2 of the second transistor TR2 are connected to a first memory-cell-selecting line,
(E) the second region SC2 is connected to a predetermined potential,
(F) the fourth region SC4 is connected to a second memory cell-selecting line, and
(G) the fifth region SC5 is connected to a second predetermined potential.
In a variant of the semiconductor memory cell according to the fourth aspect of the present invention, the fifth region SC5 may be connected to the first region SC1, in place of being connected to the second predetermined potential.
The semiconductor memory cell according to the fourth aspect of the present invention including the above variant preferably has a configuration in which a junction portion of the third region SC3 and the fourth region SC4 forms a diode D, and one source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line through the diode D.
For achieving the above object, according to a fifth aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control,
said semiconductor memory cell having;
(a) a first semi-conductive region SC1 having a second conductivity type,
(b) a second semi-conductive or conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 forming a rectifier junction together with the first region SC1,
(c) a third semi-conductive region SC3 formed in a surface region of the first region SC1 and spaced from the second region SC2, said third region SC3 having a first conductivity type,
(d) a fourth semi-conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 having the second conductivity type, and
(e) a gate region G shared by the first transistor TR1 and the second transistor TR2 and formed on a barrier layer so as to bridge the second region SC2 and the third region SC3 and so as to bridge the first region SC1 and the fourth region SC4,
wherein;
(A-1) source/drain regions of the first transistor TR1 are constituted of the second region SC2 and a surface region of the third region SC3 which surface region is sandwiched by the first region SC1 and the fourth region SC4,
(A-2) a channel forming region CH1 of the first transistor TR1 is constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(B-1) source/drain regions of the second transistor TR2 are constituted of the first region SC1 and the fourth region SC4,
(B-2) a channel forming region CH2 of the second transistor TR2 is constituted of a surface region of the third region SC3 which surface region corresponds to (or functions as) one source/drain region of the first transistor TR1 and is sandwiched by the first region SC1 and the fourth region SC4,
(C-1) gate regions of the junction-field-effect transistor TR3 are constituted of the fourth region SC4 and a portion of the first region SC1 facing the fourth region SC4,
(C-2) a channel region CH3 of the junction-field-effect transistor TR3 is constituted of part of the third region SC3 positioned under one source/drain region of the second transistor TR2 and sandwiched by the first region SC1 and the fourth region SC4,
(C-3) one source/drain region of the junction-field-effect transistor TR3 is constituted of a surface region of the third region SC3 which surface region extends from one end of the channel region CH3 of the junction-field-effect transistor TR3, corresponds to (or functions as) one source/drain region of the first transistor TR1, corresponds to (or functions as) the channel forming region CH2 of the second transistor TR2 and is sandwiched by the first region SC1 and the fourth region SC4,
(C-4) the other source/drain region of the junction-field-effect transistor TR3 is constituted of the third region SC3 extending from the other end of the channel region CH3 of the junction-field-effect transistor TR3,
(D) the gate region G is connected to a first memory-cell-selecting line,
(E) the second region SC2 is connected to a predetermined potential, and
(F) the fourth region SC4 is connected to a second memory-cell-selecting line.
The semiconductor memory cell according to the fifth aspect of the present invention further may have a fifth conductive region SC5 which is formed in a surface region of the third region SC3 and forms a rectifier junction together with the third region SC3, and preferably has a configuration in which a diode D is formed of the fifth region SC5 and the third region SC3 and in which the third region SC3 corresponding to (or functioning as) the other source/drain region of the junction-field-effect transistor TR3 is connected to the second memory-cell-selecting line through the diode D.
For achieving the above object, according to a sixth aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control,
said semiconductor memory cell having;
(a) a first semi-conductive region SC1 having a second conductivity type,
(b) a second semi-conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 having a first conductivity type,
(c) a third semi-conductive region SC3 formed in a surface region of the first region SC1 and spaced from the second region SC2, said third region SC3 having the first conductivity type,
(d) a fourth semi-conductive or conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 forming a rectifier junction together with the third region SC3,
(e) a fifth semi-conductive or conductive region SC5 formed in a surface region of the second regions SC2, said fifth region SC5 forming a rectifier junction together with the second region SC2, and
(f) a gate region G shared by the first transistor TR1 and the second transistor TR2 and formed on a barrier layer so as to bridge the second region SC2 and the third region SC3 and so as to bridge the first region SC1 and the fourth region SC4,
wherein;
(A-1) source/drain regions of the first transistor TR1 are constituted of the second region SC2 and a surface region of the third region SC3 which surface region is sandwiched by the first region SC1 and the fourth region SC4,
(A-2) a channel forming region CH1 of the first transistor TR1 is constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(B-1) source/drain regions of the second transistor TR2 are constituted of the first region SC1 and the fourth region SC4,
(B-2) a channel forming region CH2 of the second transistor TR2 is constituted of a surface region of the third region SC3 which surface region corresponds to (or functions as) one source/drain region of the first transistor TR1 and is sandwiched by the first region SC1 and the fourth region SC4,
(C-1) gate regions of the junction-field-effect transistor TR3 are constituted of the fifth region SC5 and a portion of the first region SC1 facing the fifth region SC5,
(C-2) a channel region CH3 of the junction-field-effect transistor TR3 is constituted of part of the second region SC2 sandwiched by the fifth region SC5 and said portion of the first region SC1,
(C-3) one source/drain region of the junction-field-effect transistor TR3 is constituted of the second region SC2 which extends from one end of the channel region CH3 of the junction-field-effect transistor TR3 and corresponds to (or functions as) one source/drain region of the first transistor TR1,
(C-4) the other source/drain region of the junction-field-effect transistor TR3 is constituted of the second region SC2 extending from the other end of the channel region CH3 of the junction-field-effect transistor TR3,
(D) the gate region G is connected to a first memory-cell-selecting line,
(E) the second region SC2 is connected to a predetermined potential,
(F) the fourth region SC4 is connected to a second memory cell-selecting line, and
(G) the fifth region SC5 is connected to a second predetermined potential.
The semiconductor memory cell according to the sixth aspect of the present invention further may have a sixth conductive region SC6 which is formed in a surface region of the third region SC3 and forms a rectifier junction together with the third region SC3, and preferably has a configuration in which a diode D is formed of the sixth region SC6 and the third region SC3 and in which the third region SC3 corresponding to (or functioning as) the other source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line through the diode D.
Further, a variant of the semiconductor memory cell according to the sixth aspect of the present invention preferably has a configuration in which the fifth region SC5 is connected to the first region SC1, in place of being connected to the second predetermined potential. In this case, the semiconductor memory cell further may have a sixth conductive region SC6 which is formed in a surface region of the third region SC3 and forms a rectifier junction together with the third region SC3, and preferably has a configuration in which a diode D is formed of the sixth region SC6 and the third region SC3 and in which the third region SC3 corresponding to (or functioning as) the other source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line through the diode D.
For achieving the above object, according to a seventh aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, a junction-field-effect transistor TR3 of a first conductivity type for current control, and a third transistor TR4 of a second conductivity type for write-in,
said semiconductor memory cell having;
(a) a first semi-conductive region SC1 having a second conductivity type,
(b) a second semi-conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 having a first conductivity type,
(c) a third semi-conductive region SC3 formed in a surface region of the first region SC1 and spaced from the second region SC2, said third region SC3 having the first conductivity type,
(d) a fourth semi-conductive or conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 forming a rectifier junction together with the third region SC3,
(e) a fifth semi-conductive or conductive region SC5 formed in a surface region of the second region SC2, said fifth region SC5 forming a rectifier junction together with the second region SC2, and
(f) a gate region G shared by the first transistor TR1, the second transistor TR2 and the third transistor TR4 and formed on a barrier layer so as to bridge the first region SC1 and the fourth region SC4, so as to bridge the second region SC2 and the third region SC3 and so as to bridge the third region SC3 and the fifth region SC5,
wherein;
(A-1) source/drain regions of the first transistor TR1 are constituted of the second region SC2 and a surface region of the third region SC3 which surface region is sandwiched by the first region SC1 and the fourth region SC4,
(A-2) a channel forming region CH1 of the first transistor TR1 is constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(B-1) source/drain regions of the second transistor TR2 are constituted of the first region SC1 and the fourth region SC4,
(B-2) a channel forming region CH2 of the second transistor TR2 is constituted of a surface region of the third region SC3 which surface region corresponds to (or functions as) one source/drain region of the first transistor TR1 and is sandwiched by the first region SC1 and the fourth region SC4,
(C-1) gate regions of the junction-field-effect transistor TR3 are constituted of the fifth region SC5 and a portion of the first region SC1 facing the fifth region SC5,
(C-2) a channel region CH3 of the junction-field-effect transistor TR3 is constituted of part of the second region SC2 sandwiched by the fifth region SC5 and said portion of the first region SC1,
(C-3) one source/drain region of the junction-field-effect transistor TR3 is constituted of the second region SC2 which extends from one end of the channel region CH3 of the junction-field-effect transistor TR3 and corresponds to (or functions as) one source/drain region of the first transistor TR1,
(C-4) the other source/drain region of the junction-field-effect transistor TR3 is constituted of the second region SC2 extending from the other end of the channel region CH3 of the junction-field-effect transistor TR3,
(D-1) one source/drain region of the third transistor TR4 is constituted of the surface region of the first region SC1 corresponding to (or functioning as) the channel forming region CH1 of the first transistor TR1,
(D-2) the other source/drain region of the third transistor TR4 is constituted of the fifth region SC5,
(D-3) a channel forming region CH4 of the third transistor TR4 is constituted of the second region SC2 corresponding to (or functioning as) one source/drain region of the first transistor TR1,
(E) the gate region G is connected to a first memory-cell-selecting line,
(F) the second region SC2 is connected to a predetermined potential, and
(G) the fourth region SC4 is connected to a second memory cell-selecting-line.
For achieving the above object, according to a eighth aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control,
said semiconductor memory cell having;
(a) a third semi-conductive region SC3 having a first conductivity type,
(b) a fourth semi-conductive or conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 forming a rectifier junction together with the third region SC3,
(c) a first semi-conductive region SC1 formed in a surface region of the third region SC3 and spaced from the fourth region SC4, said first region SC1 having a second conductivity type,
(d) a second semi-conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 having the first conductivity type,
(e) a fifth semi-conductive or conductive region SC5 formed in a surface region of the second region SC2, said fifth region SC5 forming a rectifier junction together with the second region SC2, and
(f) a gate region G shared by the first transistor TR1 and the second transistor TR2 and formed on a barrier layer so as to bridge the second region SC2 and the third region SC3 and so as to bridge the first region SC1 and the fourth region SC4,
wherein;
(A-1) source/drain regions of the first transistor TR1 are constituted of the second region SC2 and the third region SC3,
(A-2) a channel forming region CH1 of the first transistor TR1 is constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(B-1) source/drain regions of the second transistor TR2 are constituted of the first region SC1 and the fourth region SC4,
(B-2) a channel forming region CH2 of the second transistor TR2 is constituted of a surface region of the third region SC3 sandwiched by the first region SC1 and the fourth region SC4,
(C-1) gate regions of the junction-field-effect transistor TR3 are constituted of the fifth region SC5 and a portion of the first region SC1 facing the fifth region SC5,
(C-2) a channel region CH3 of the junction-field-effect transistor TR3 is constituted of part of the second region SC2 sandwiched by the fifth region SC5 and said portion of the first region SC1,
(C-3) source/drain regions of the junction-field-effect transistor TR3 are constituted of the second region SC2 extending from both ends of the channel region CH3 of the junction-field-effect transistor TR3,
(D) the gate region G is connected to a first memory-cell-selecting line,
(E) the second region SC2 is connected to a predetermined potential,
(F) the fourth region SC4 is connected to a second memory-cell-selecting line, and
(G) the fifth region SC5 is connected to a second predetermined potential.
The semiconductor memory cell according to the eighth aspect of the present invention may have a configuration in which the fifth region SC5 is connected to the first region SC1, in place of being connected to the second predetermined potential. Further, the semiconductor memory cell according to the eighth aspect of the present invention may have a configuration in which a junction portion of the third region SC3 and the fourth region SC4 forms a diode D, and one source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line through the diode D. Further, the semiconductor memory cell according to the eighth aspect of the present invention may have a sixth conductive region SC6 which is formed in a surface region of the third region SC3 and forms a rectifier junction together with the third region SC3, and preferably has a configuration in which a diode D is formed of the sixth region SC6 and the third region SC3 and in which the third region SC3 corresponding to (or functioning as) the other source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line through the diode D.
For achieving the above object, according to a ninth aspect of the present invention, there is provided a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, a junction-field-effect transistor TR3 of a first conductivity type for current control, and a third transistor TR4 of a second conductivity type for write-in,
said semiconductor memory cell having;
(a) a third semi-conductive region SC3 having a first conductivity type,
(b) a fourth semi-conductive or conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 forming a rectifier junction together with the third region SC3,
(c) a first semi-conductive region SC1 formed in a surface region of the third region SC3 and spaced from the fourth region SC4, said first region SC1 having a second conductivity type,
(d) a second semi-conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 having the first conductivity type,
(e) a fifth semi-conductive or conductive region SC5 formed in a surface region of the second region SC2, said fifth region SC5 forming a rectifier junction together with the second region SC2, and
(f) a gate region G shared by the first transistor TR1, the second transistor TR2 and the third transistor TR4 and formed on a barrier layer so as to bridge the first region SC1 and the fourth region SC4, so as to bridge the second region SC2 and the third region SC3 and so as to bridge the third region SC3 and the fifth region SC5,
wherein;
(A-1) source/drain regions of the first transistor TR1 are constituted of the second region SC2 and a surface region of the third region SC3 which surface region is sandwiched by the first region SC1 and the fourth region SC4,
(A-2) a channel forming region CH1 of the first transistor TR1 is constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
(B-1) source/drain regions of the second transistor TR2 are constituted of the first region SC1 and the fourth region SC4,
(B-2) a channel forming region CH2 of the second transistor TR2 is constituted of a surface region of the third region SC3 which surface region corresponds to (or functions as) one source/drain region of the first transistor TR1 and is sandwiched by the first region SC1 and the fourth region SC4,
(C-1) gate regions of the junction-field-effect transistor TR3 are constituted of the fifth region SC5 and a portion of the first region SC1 facing the fifth region SC1,
(C-2) a channel region CH3 of the junction-field-effect transistor TR3 is constituted of part of the second region SC2 sandwiched by the fifth region SC5 and said portion of the first region SC1,
(C-3) one source/drain region of the junction-field-effect transistor TR3 is constituted of the second region SC2 which extends from one end of the channel region CH3 of the junction-field-effect transistor TR3 and corresponds to (or functions as) one source/drain region of the first transistor TR1,
(C-4) the other source/drain region of the junction-field-effect transistor TR3 is constituted of the second region SC2 extending from the other end of the channel region CH3 of the junction-field-effect transistor TR3,
(D-1) one source/drain region of the third transistor TR4 is constituted of the surface region of the first region SC1 corresponding to (or functioning as) the channel forming region CH1 of the first transistor TR1,
(D-2) the other source/drain region of the third transistor TR4 is constituted of the fifth region SC5,
(D-3) a channel forming region CH4 of the third transistor TR4 is constituted of the second region SC2 corresponding to (or functioning as) one source/drain region of the first transistor TR1,
(E) the gate region G is connected to a first memory-cell-selecting line,
(F) the second region SC2 is connected to a predetermined potential, and
(G) the fourth region SC4 is connected to a second memory-cell-selecting line.
The semiconductor memory cell according to the ninth aspect of the present invention may have a configuration in which a junction portion of the third region SC3 and the fourth region SC4 forms a diode D, and one source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line through the diode D. Further, the semiconductor memory cell according to the ninth aspect of the present invention may have a sixth conductive region SC6 which is formed in a surface region of the third region SC3 and forms a rectifier junction together with the third region SC3, and preferably has a configuration in which a diode D is formed of the sixth region SC6 and the third region SC3 and in which the third region SC3 corresponding to (or functioning as) the other source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line through the diode D.
The semiconductor memory cell of the present invention can be formed in a surface region of a semiconductor substrate, on an insulating layer formed on a semiconductor substrate, in a well of the second conductivity type formed in a semiconductor substrate (in the first to seventh aspects of the present invention), in a well of the first conductivity type formed in a semiconductor substrate (in the eighth and ninth aspects of the present innovation), or on an electric insulator, and is preferably formed in a well or formed on an insulator including an insulating layer and an insulating substrate for preventing xcex1-ray soft error.
The junction-field-effect transistor (JFET) TR3 in the semiconductor memory cell of the present invention can be formed by
(1) optimizing the distance between the facing gate regions of the junction-field-effect transistor TR3, that is, the thickness of the channel region CH3, and
(2) optimizing impurity concentrations of the facing gate regions and the channel region CH3 of the junction-field-effect transistor TR3. It should be noted that if neither the distance between the facing gate regions (the thickness of the channel region CH3) of the junction-field-effect transistor TR3, nor the impurity concentrations of the facing gate regions and the channel region CH3 of the junction-field-effect transistor TR3 are optimized, the depletion layer will not widened, making it impossible to bring the junction-field-effect transistor TR3 into an on-state or an off-state. These optimization need to be carried out by computer simulation or experiments.
For achieving the above object, according to the first aspect of the present invention, there is provided a method for manufacturing a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control, said semiconductor memory cell having;
(a) a first semi-conductive region SC1 having a second conductivity type,
(b) a second semi-conductive or conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 forming a rectifier junction together with the first region SC1,
(c) a third semi-conductive region SC3 formed in a surface region of the first region SC1 and spaced from the second region SC2, said third region SC3 having a first conductivity type,
(d) a fourth semi-conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 having the second conductivity type, and
(e) a gate region G shared by the first transistor TR1 and the second transistor TR2 and formed on a barrier layer so as to bridge the second region SC2 and the third region SC3 and so as to bridge the first region SC1 and the fourth region SC4, the first transistor TR1 having;
(A-1) source/drain regions constituted of the second region SC2 and a surface region of the third region SC3 which surface region is sandwiched by the first region SC1 and the fourth region SC4, and
(A-2) a channel forming region CH1 constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
the second transistor TR2 having;
(B-1) source/drain regions constituted of the first region SC1 and the fourth region SC4, and
(B-2) a channel forming region CH2 constituted of a surface region of the third region SC3 which surface region corresponds to (or functions as) one source/drain region of the first transistor TR1 and is sandwiched by the first region SC1 and the fourth region SC4, and
the junction-field-effect transistor TR3 having;
(C-1) gate regions constituted of the fourth region SC4 and a portion of the first region SC1 facing the fourth region SC4,
(C-2) a channel region CH3 constituted of part of the third region SC3 positioned under one source/drain region of the second transistor TR2 and sandwiched by the first region SC1 and the fourth region SC4,
(C-3) one source/drain region constituted of a surface region of the third region SC3 which surface region extends from one end of the channel region CH3 of the junction-field-effect transistor TR3, corresponds to (or functions as) one source/drain region of the first transistor TR1, corresponds to (or functions as) the channel forming region CH2 of the second transistor TR2 and is sandwiched by the first region SC1 and the fourth region SC4, and
(C-4) the other source/drain region constituted of the third region SC3 extending from the other end of the channel region CH3 of the junction-field-effect transistor TR3,
said method comprising;
(1) forming the barrier layer on the surface of the first region SC1, and then, forming the gate region G on the barrier layer, and
(2) forming the first region SC1, the third region SC3 and the fourth region SC4 by ion implantation in an arbitrary order so as to optimize a distance between the facing gate regions of the junction-field-effect transistor TR3 and so as to optimize impurity concentrations of the facing gate regions and the channel region CH3 of the junction-field-effect transistor TR3.
For achieving the above object, according to the second aspect of the present invention, there is provided a method for manufacturing a semiconductor memory cell comprising a first transistor TR1 of a first conductivity type for read-out, a second transistor TR2 of a second conductivity type for write-in, and a junction-field-effect transistor TR3 of a first conductivity type for current control,
said semiconductor memory cell having;
(a) a first semi-conductive region SC1 having a second conductivity type,
(b) a second semi-conductive region SC2 formed in a surface region of the first region SC1, said second region SC2 having a first conductivity type,
(c) a third semi-conductive region SC3 formed in a surface region of the first region SC1, and spaced from the second region SC2, said third region SC3 having the first conductivity type,
(d) a fourth semi-conductive or conductive region SC4 formed in a surface region of the third region SC3, said fourth region SC4 forming a rectifier junction together with the third region SC3,
(e) a fifth semi-conductive or conductive region SC5 formed in a surface region of the second region SC2, said fifth region SC5 forming a rectifier junction together with the second region SC2, and
(f) a gate region G shared by the first transistor TR1 and the second transistor TR2 and formed on a barrier layer so as to bridge the second region SC2 and the third region SC3 and so as to bridge the first region SC1 and the fourth region SC4,
the first transistor TR1 having;
(A-1) source/drain regions constituted of the second region SC2 and a surface region of the third region SC3 which surface region is sandwiched by the first region SC1 and the fourth region SC4, and
(A-2) a channel forming region CH1 constituted of a surface region of the first region SC1 sandwiched by the second region SC2 and the third region SC3,
the second transistor TR2 having;
(B-1) source/drain regions constituted of the first region SC1 and the fourth region SC4, and
(B-2) a channel forming region CH2 constituted of a surface region of the third region SC3 which surface region corresponds to (or functions as) one source/drain region of the first transistor TR1 and is sandwiched by the first region SC1 and the fourth region SC4, and
the junction-field-effect transistor TR3 having;
(C-1) gate regions constituted of the fifth region SC5 and a portion of the first region SC1 facing the fifth region SC5,
(C-2) a channel region CH3 constituted of part of the second region SC2 sandwiched by the fifth region SC5 and said portion of the first region SC1,
(C-3) one source/drain region constituted of the second region SC2 which extends from one end of the channel region CH3 of the junction-field-effect transistor TR3 and corresponds to (or functions as) one source/drain region of the first transistor TR1, and
(C-4) the other source/drain region constituted of the second region SC2 extending from the other end of the channel region CH3 of the junction-field-effect transistor TR3,
said method comprising;
(1) forming the barrier layer on the surface of the first region SC1, and then, forming the gate region G on the barrier layer, and
(2) forming the first region SC1, the second region SC2 and the fifth region SC5 by ion implantation in an arbitrary order so as to optimize a distance between the facing gate regions of the junction-field-effect transistor TR3 and so as to optimize impurity concentrations of the facing gate regions and the channel region CH3 of the junction-field-effect transistor TR3.
In the semiconductor memory cell according to any one of the third to ninth aspects of the present invention, a region SC7 containing a high concentration of an impurity having the first conductivity type is preferably formed under the first region SC1, for increasing a potential or an electric charge stored in the channel forming region CH1 of the first transistor TR1.
The channel forming region or the channel region can be formed from a material such as silicon or GaAs by using a known process. Each gate region can be formed of a material such as a metal, a silicide, GaAs doped with an impurity at a high concentration, silicon, amorphous silicon or polysilicon doped with an impurity, or a polyside by using a known process. The barrier layer can be formed of a material such as SiO2, Si3N4, Al2O3 or GaAlAs by using a known process. Each region can be formed of silicon, amorphous silicon or polysilicon doped with an impurity, a silicide, a two-layer structure having a silicide layer and a semi-conductive layer, or GaAs doped with an impurity at a high concentration by using a known process, depending on characteristics required.
When each region in the semiconductor memory cell according to any one of the third to ninth aspects of the present invention is constituted of a conductive region, it can be formed of a silicide, a metal such as Mo or Al, or a metal compound. When the sixth conductive region SC6 is formed in the semiconductor memory cell according to the third aspect of the present invention, preferably, the fifth region SC5 is constituted of a semi-conductive region. Further, when the sixth conductive region SC6 is formed in the semiconductor memory cell according to the sixth or seventh aspect of the present invention, preferably, the fourth region SC4 is constituted of a semi-conductive region. Moreover, when the sixth conductive region SC6 is formed in the semiconductor memory cell according to the eighth or ninth aspect of the present invention, preferably, the fourth region SC4 is constituted of a semi-conductive region.
In the semiconductor memory cell of the present invention, each gate region of the first transistor TR1 and the second transistor TR2 is connected to the first memory-cell-selecting line. It is therefore sufficient to provide one first memory-cell-selecting line, so that the chip area can be decreased.
In the semiconductor memory cell according to the third aspect or the fourth aspect of the present invention, the first region SC1 corresponding to (or functioning as) one source/drain region of the second transistor TR2 corresponds to (or functions as) the channel forming region CH1 of the first transistor TR1. When information is written in, the second transistor TR2 is brought into an on-state, and as a result, the information is stored in the channel forming region CH1 of the first transistor TR1 as a potential or an electric charge. When the information is read out, the threshold voltage of the first transistor TR1 seen from the gate region varies depending upon the potential or the electric charge (the information) stored in the channel forming region CH1 of the first transistor TR1. Therefore, when the information is read out, the storage state of the first transistor TR1 can be judged from the magnitude of a channel current (including a zero magnitude) by applying a properly selected potential to the gate region. That is, the information is read out by detecting the operation state of the first transistor TR1.
In the semiconductor memory cell according to any one of the fifth to ninth aspects of the present invention, the first region SC1 corresponding to (or functioning as) one source/drain region of the second transistor TR2 corresponds to (or functions as) the channel forming region CH1 of the first transistor TR1. Further, the third region SC3 corresponding to (or functioning as) the channel forming region CH2 of the second transistor TR2 and corresponding to (or functioning as) the source/drain region of the first transistor TR1 is connected to the second memory-cell-selecting line, for example, through the diode D, or connected to the information read-out line. And, a potential in the second memory-cell-selecting line is properly selected, whereby the threshold voltage of the first transistor TR1 seen from the gate region can be allowed to vary at a read-out time. As a result, the on- and off-states of the first transistor TR1 and the second transistor TR2 can be controlled by properly selecting a potential in the first memory-cell-selecting line.
That is, when the potential of the first memory-cell-selecting line of the semiconductor memory cell of the present invention is set at a potential at which the second transistor TR2 is sufficiently brought into an on-state at a write-in time, an electric charge is charged in a capacitor formed between the first region SC1 and the third region SC3 in the second transistor TR2 depending upon the potential of the second memory-cell-selecting line. As a result, information is stored in the channel forming region CH1 (the first region SC1) of the first transistor TR1 as a potential difference between the first region SC1 and the third region SC3 or as an electric charge. When the information is read out, the potential of the third region SC3 is set at a read-out potential, and in the first transistor TR1, the potential or the electric charge (the information) stored in the channel forming region CH1 is converted to a potential difference between the first region SC1 corresponding to (or functioning as) the channel forming region CH1 and the second region SC2 corresponding to (or functioning as) the source/drain region or to an electric charge. As a result, the threshold voltage of the first transistor TR1 seen from the gate region varies depending upon the above potential difference or electric charge (the information). When the information is read out, therefore, the on/off operation of the first transistor TR1 can be controlled by applying a properly selected potential to the gate region. That is, the information can be read out by detecting the operation state of the first transistor TR1.
Moreover, the semiconductor memory cell of the present invention is provided with the junction-field-effect transistor TR3 in addition to the first transistor TR1 and the second transistor TR2. Since the on/off operation of the junction-field-effect transistor TR3 is controlled when the information is read out, a large margin can be left for the current which flows between the second region SC2 and the third region SC3. As a result, the number of semiconductor memory cells that can be connected to the second memory-cell-selecting line is hardly limited, and further, the information holding time (retention time) of the semiconductor memory cell can be increased.
Further, when the diode D is provided, the information read-out line connected to the other source/drain region of the junction-field-effect transistor TR3 can be omitted. Meanwhile, when the diode is constituted of a pn junction in the semiconductor memory cell of the present invention, and if the potential setting in each region constituting the diode or the designing of impurity concentration relationships in each region is improper, xe2x80x9clatch-upxe2x80x9d may take place when the information is read out. Otherwise, a bipolar pnp transistor constituted of the fourth region SC4, the third region SC3 and the first region SC1 is brought into an on-state, and the information stored in the first region SC1 may leak. For avoiding the above problems, the voltage which is applied to the second memory-cell-selecting line when the information is read out is required to be a low degree of voltage (0.4 volt or lower in a case of a pn junction) at which no large forward current flows in the junction portion of the fourth region SC4 and the third region SC3. The above problems can be overcome, for example, by a method in which the fifth region SC5 in the semiconductor memory cell according to the fifth aspect of the present invention or the sixth region SC6 in the semiconductor memory cell according to the sixth or seventh aspect of the present invention is formed in the surface region of the third region SC3, a silicide, a metal or a metal compound is used to constitute the fifth region SC5 or the sixth region SC6, and the junction between the fifth region SC5 or the sixth region SC6 in an embodiment according to the above aspect of the present invention and the third region SC3 is formed as a junction in which a larger number of carriers mainly constitute a forward current like a Schottky junction. That is, the fifth region SC5 or the sixth region SC6 in an embodiment according to the above aspect of the present invention is constituted of a silicide layer, a metal layer formed of Mo, Al or the like, or a metal compound layer, and a diode of a Schottky junction type is formed, whereby the risk of latch-up can be avoided, and the limitation on the voltage applied to the second memory-cell-selecting line is no longer necessary, or the information retention time can be increased. In some case, the fifth region SC5 and the sixth region SC6 in embodiments according to the above aspects of the present invention may be constituted of a semiconductor layer of the second conductivity type, and a diode of a pn junction type may be formed.
The semiconductor memory cell of the present invention retains the information as a potential, a potential difference or an electric charge, while leak current caused by junction leak, etc., attenuates them sooner or later. It is therefore necessary to refresh it, and the semiconductor memory cell is operated like DRAM.
In the semiconductor memory cell according to any one of the first to ninth aspects of the present invention, the wiring configuration can be simplified by connecting the fifth region SC5 to the first region SC1. In the embodiments according to the fifth to ninth aspects of the present invention, further, the first transistor TR1 and the second transistor TR2 are merged into one unit, and the cell area and the leak current can be decreased.
In the semiconductor memory cell according to the seventh or ninth aspect of the present invention, the third transistor TR4 for write-in is provided in addition to the junction-field-effect transistor TR3, and when the information is read out, the on/off operation of the third transistor TR4 is controlled. A very large margin can be therefore reliably provided for a current which flows between the second region SC2 and the third region SC3. As a result, the limitation on the number of semiconductor memory cells that can be connected to the second memory-cell-selecting line can be further decreased.